Integrated circuits are interconnected on a circuit board via signal path interconnects to form circuits. During circuit operation, the integrated circuits transfer data and control information between one another via the signal path interconnects. For proper circuit operation, the signal path interconnects must be free of faults, such as open circuit or short circuit condition. Techniques such as boundary scan are commonly implemented in integrated circuits to test for short and open conditions on the signal path interconnects between integrated circuits.
However, time related faults, referred to as "delay faults," on signal path interconnects cannot be tested adequately using standard boundary scan techniques. A delay fault is neither an open or short circuit fault, and may exist on a signal path that is electrically intact. A delay fault occurs when the time necessary for a signal to propagate from the driving source to a receiving source exceeds a prescribed time.
While a boundary test approach may be used for testing the integrity of wiring interconnects between integrated circuits, it cannot be used effectively to test for timing delay problems that may occur between an output buffer of a driving integrated circuit and an input buffer of a receiving integrated circuit. To test for signal path time delays, data must be applied from the outputs from one integrated circuit and be sampled into the inputs of another integrated circuits in a short period of time. A boundary scan approach to performing delay tests is ineffective because of the length of time between applying data to an integrated circuit's output and sampling the output into a neighboring integrated circuit's input.
For example, in the proposed IEEE boundary scan standard, the minimum number of test clocks between a time at which data may be output from one integrated circuit to when it may be sampled into another integrated circuit is 1 1/2 test clocks. At a 10 MHz test clock rate, the combinational logic delay between the driving integrated circuit and the receiving integrated circuit would have to be greater than 150 nanoseconds to be detected as a delay related failure. This level of timing resolution is inadequate to test combinational logic or other types of delay faults in the signal path interconnects between integrated circuits.
Therefore, a need has arisen in the industry for a method and apparatus for testing delay faults between integrated circuits.